학술논문
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution
Document Type
Conference
Author
Source
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC) Solid-State Circuits Conference (A-SSCC), 2021 IEEE Asian. :1-3 Nov, 2021
Subject
Language
Abstract
In this work, an energy- and area-efficient Display Stream Compression (DSC) encoder architecture is proposed for energy-constrained systems driving high-resolution internal/external display (e.g., virtual reality headsets, smartphones). As main motivation, relentlessly higher resolutions in video displays (e.g., 4K, 8K) require very high uncompressed processor-display data rates of 30 Gbps for 4K (120 Gbps for 8K) at 120 frames per second (fps) and 10 bits per component (bpc). The data transfer bandwidth to the display cannot keep pace with such demand, making compression a necessity.