학술논문
A 7-nm 6R6W Register File With Double-Pumped Read and Write Operations for High-Bandwidth Memory in Machine Learning and CPU Processors
Document Type
Periodical
Author
Source
IEEE Solid-State Circuits Letters IEEE Solid-State Circuits Lett. Solid-State Circuits Letters, IEEE. 1(12):225-228 Dec, 2018
Subject
Language
ISSN
2573-9603
Abstract
A 7-nm register file (RF) with a 16-transistor (16T) 3-read and 3-write (3R3W) bitcell double pump or time multiplexes the read and write access ports twice per clock cycle to achieve 6-read and 6-write (6R6W) operations per cycle for high-bandwidth (BW) on-die memory in high-performance machine learning and CPU processors. From silicon test-chip measurements at 0.9 V, the double-pumped (DP) 6R6W RF trades off a 19% lower maximum clock frequency ( $F_{\mathrm{ MAX}}$ ) for $2\times $ the number of read and write operations per cycle, resulting in a 62% higher memory BW compared to a conventional single-access (SA) 3R3W RF.