학술논문

Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors
Document Type
Conference
Source
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the. :1-4 Sep, 2014
Subject
Components, Circuits, Devices and Systems
Error correction codes
Random access memory
Semiconductor device measurement
Measurement uncertainty
Silicon
Integrated circuit modeling
Data models
Language
ISSN
0886-5930
2152-3630
Abstract
Models for cache yield and coverage for radiation-induced soft errors quantify the trade-off between the minimum supply voltage (V MIN ) and the soft-error protection when applying error-correcting codes (ECC) to a cache. Model predictions of the V MIN benefit and soft-error coverage agree closely with silicon measurements from a 7Mb data cache in a 20nm test chip when considering either single-error correction, double-error detection (SECDED) or double-error correction, triple-error detection (DECTED) codes. Silicon measurements demonstrate a V MIN reduction of 19% and 27% from SECDED and DECTED, respectively, as compared to a cache without ECC. Moreover, silicon measurements highlight a salient insight in that only 0.12% of the cache words contain an error when operating at the cache V MIN with SECDED. Thus, SECDED simultaneously enables a 19% lower V MIN and 99.88% coverage for radiation-induced soft errors. Model projections indicate larger benefits in V MIN and soft-error protection as future cache sizes increase.