부산대학교 도서관

The micro telecommunications computing architecture (MTCA) standard is widely used in developing advanced data acquisition and processing solutions in the big physics community. The number of applications implemented using commercial advanced mezzanine cards (AMC) using AMD-Xilinx and Intel field-programmable gate array (FPGA) systems on chip is growing due to the flexibility and scalability of these reconfigurable hardware devices and their suitability to implement intelligent applications using artificial intelligence and machine learning techniques. This article presents the specific design methodologies for hardware acceleration proposed by both FPGA manufacturers. Comparative results are obtained from two different software/hardware setups using two different AMCs, one based on Intel FPGA Arria 10 and another based on Xilinx ZynqMP. This article illustrates the process of how to modify the board support package, required by the hardware acceleration methodology, to implement the JESD204B and low-voltage differential signaling (LVDS) interfaces with the FPGA mezzanine card (FMC) modules containing the ADCs, to prepare the AMC cards to implement such kind of applications. The data acquisition and processing implementation inside these reference designs, with both languages OpenCL and high-level synthesis (HLS), is described. An important feature, needed for many applications in the big physics field, is the interface with the Experimental Physics and Industrial Control System (EPICS) software framework using the ITER Nominal Device Support (NDS) framework, which is briefly described.