부산대학교 도서관

Silicon-based charge trapping memory (CTM) devices currently dominate the nonvolatile memory (NVM) technology due to their excellent reliability, scalability, and maturity of the manufacturing process; however, they are rigid, which limits their potential in futuristic applications, such as wearables and flexible displays, among many others; moreover, the majority of previously reported studies on flexible NVM have been limited to either nonsilicon-based CTM or to emerging NVM technologies, such as ferroelectric random access memory and memristors, among others, which still need to overcome different challenges, including, but not limited to, reliability issues and complementary metal–oxide-semiconductor (CMOS) compatibility. In this article, a flexible silicon-based CTM device is developed using a volumetric reduction process. A MOS memory structure with a 7-nm thin Si3N4 layer embedded between 5-nm tunneling (SiO2) and 9-nm blocking oxides (Al2O3) is first fabricated. Next, a backside sequential etching process transforms the rigid die into an ultrathin ( $20~\mu \text{m}$ ) flexible Si die for future application in flexible electronics. The fabricated two-terminal device exhibits a 2.32 V memory window in both rigid and bent states, as observed using capacitance–voltage measurements. A three-terminal version of the device was also developed, where the source and drain terminals were activated using an in situ doped plasma-enhanced CVD (PECVD) process. The flexible encapsulated chip was tested using current–voltage measurements, and the performance was compared at different mechanical bending conditions. The electrical characterization confirms that the flexible devices show similar endurance (104 cycles) and retention (105s) performances to their rigid counterparts.