학술논문
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements
Document Type
Periodical
Author
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 47(1):97-106 Jan, 2012
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 $\mu\hbox{m}^{2}$ bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 V ${\rm VDD}_{\rm MIN}$ operation is enabled by three assist features. Stability is improved by a bit-line regulation scheme which reduces charge injection into the bit-cell. Enhancements to the write path include an increase of 40% of bit-line boost voltage. Finally, a bit-cell-tracking delay circuit improves both performance and yield across the process space.