부산대학교 도서관

Several recent studies have proposed the utilization of emerging technology devices, such as ReRAM, spintronic, and phase change memory in hardware-implemented neural network designs. However, the current poor maturity of the manufacturing process of memristive devices limits the implementation of synapses to low precision weights and to smaller size crossbars, which could be an issue for complex, higher dimensions machine vector learning tasks (e.g., object recognition, classifications, etc). Face to these challenges, efficient hardware implementations use binarization for weights and activation functions in the attempt to reach better energy efficiency, reduce the utilization of memory and the execution time. Moreover, to compensate the immaturity of the emerging devices technology and achieve better convergence, accuracy, and speed for learning and inference process, the neural network has to be designed either with an increased degree of redundancy, or with error correction capabilities. To avoid the inherent hardware cost of the redundancy and counteract the aforementioned issues, we propose an approach combining the concept of Ensemble Neural Networks paradigm with analog in-memory hardware implementation with spin-orbit torque (SOT) spintronic devices. These devices are among the most power-efficient emerging technologies. The architectural performances, power, and accuracy are verified on several datasets, showing that these combined approaches allow not only a very good resilience to high bit error rates but also a great reduction in execution time and number of memory accesses with a further reduction of $\times 100$ for the energy consumption thanks to the SOT spintronic-based device.