학술논문
A Full Current-Mode Timing Circuit with Dark Noise Suppression for the CERN CMS Experiment
Document Type
Conference
Author
Source
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Solid State Circuits Conference (ESSCIRC), ESSCIRC 2022- IEEE 48th European. :177-180 Sep, 2022
Subject
Language
Abstract
In this paper we present an analog circuit for the new MIP Timing Detector of the CMS experiment at CERN, featuring, for the first time, a silicon implementation of the Differential Leading Edge Discriminating technique to suppress SiPM dark noise. This technique also stabilizes the baseline, leading to a time resolution of 25 ps at beginning of life and 55 ps at end of life while dissipating less than 4 mW. The full analog front-end ASIC has 32 channels and has been designed in a CMOS 130 nm technology with a total die area of 8.5 x 5.2 mm2. The radiation tolerance of this design has been confirmed by radiation tests.