학술논문
Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing
Document Type
Conference
Author
Hafez, W.; Agnihotri, P.; Asoro, M.; Aykol, M.; Bains, B.; Bambery, R.; Bapna, M.; Barik, A.; Chatterjee, A.; Chiu, P.C.; Chu, T.; Firby, C.; Fischer, K.; Fradkin, M.; Greve, H.; Gupta, A.; Haralson, E.; Haran, M.; Hicks, J.; Illa, A.; Jang, M.; Klopcic, S.; Kobrinsky, M.; Kuns, B.; Lai, H.-h.; Lanni, G.; Lee, S.-H.; Lindert, N.; Lo, C.-l.; Luo, Y.; Malyavanatham, G.; Marinkovic, B.; Maymon, Y.; Nabors, M.; Neirynck, J.; Packan, P.; Paliwal, A.; Pantisano, L.; Paulson, L.; Penmatsa, P.; Prasad, C.; Puls, C.; Rahman, T.; Ramaswamy, R.; Samant, S.; Sell, B.; Sethi, K.; Shah, F.; Shamanna, M.; Shang, K.; Li, Q.; Sibakoti, M.; Stoeger, J.; Strutt, N.; Thirugnanasambandam, R.; Tsai, C.; Wang, X.; Wang, A.; Wu, S.-j.; Xu, Q.; Zhong, X.-h.; Natarajan, S.
Source
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
Subject
Language
ISSN
2158-9682
Abstract
This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with $\gt 90$% cell utilization showed $\gt 30$% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.