학술논문

Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs
Document Type
Conference
Source
2019 IEEE International Reliability Physics Symposium (IRPS) Reliability Physics Symposium (IRPS), 2019 IEEE International. :1-5 Mar, 2019
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Mesons
Single event upsets
Radiation effects
Random access memory
FinFETs
Voltage measurement
single event upset
SRAMs
muons
direct ionization
muon capture
technology scaling
Language
ISSN
1938-1891
Abstract
In this paper, we compare the negative and positive muon-induced SEU event cross sections of 28-nm and 65-nm planar bulk CMOS SRAMs. Our measurement results show a 3.6 X increase in muon-induced SEU event cross section from 65-nm to 28-nm technology, and negative muon-induced SEU event cross section is 3.3 X larger compared to positive muons at 28-nm technology. This result is consistent with the previous works reporting muon-induced SEU event cross section increases with technology scaling. The measured result also suggests the contribution of direct ionization to the total SEU event cross section is 54.1% at 28-nm node with operating voltage of 0.6 V while it is 1.8% at 65-nm node with 0.9 V.