학술논문
Zero-Temperature-Coefficient of planar and MuGFET SOI devices
Document Type
Conference
Source
2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on. :1753-1756 Nov, 2010
Subject
Language
Abstract
The Zero Temperature Coefficient (ZTC) is investigated experimentally in planar and standard/biaxially strained triple-gate nFinFETs fabricated on SOI wafers. In this work a simple model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (V ZTC ) is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations of the threshold voltage and the transconductance degradation factor. Although simple, the model predictions are in good agreement with the experimental results.