부산대학교 도서관

Abstract The capacitance mismatch problem limits the accuracy improvement of high‐precision SAR ADCs (Successive Approximation Register Analog‐to‐Digital Converters). To address the capacitance array mismatch in SAR ADCs, this paper proposes a novel capacitor calibration scheme based on the Time‐to‐Digital Converter (TDC). This scheme achieves calibration accuracy as high as 0.01% and can be flexibly designed to meet the accuracy requirements of SAR ADCs. Simulation results indicate that the capacitance mismatch issue of a redundant capacitor 13‐bit SAR ADC can be completely eliminated, and the effective number of bits (ENOB) approach the ideal value of 13.18 bits. Additionally, the analog component of this scheme utilizes four inverter chains, two D flip‐flops, and four counters, without requiring a large area for auxiliary calibration capacitors.