부산대학교 도서관

With the development of high speed communication system and the improvement of the transmission speed, Phase Lock Loop(PLL) to be the core circuit of providing precision clock has been put forward higher request, not only required to produce low jitter and low noise clock, but also demanded wide frequency range and multi-protocol supportment. As the core module of PLL, the performance of the phase noise and frequency range of voltage control oscillation(VCO) directly influence the quality of transmission clock. To reach the different transmission frequency requirement of multi-protocol, a 6.5-to-11 GHz LCVCO with wide-frequency-range and low-phase-noise is designed. Using 6-bits frequency –band-selected signal to control tuning capacitor array for relalizing the division and adjustment of the output frequency, and design optimal Kvco within each band to cover all frequency points with low phase noise. This chip is fabricated in 40 nm CMOS process, the simulation results shown that the output frequency is from 6.5 GHz to 11 GHz and the phase noise is below 107.1 dBc@1 MHz.