학술논문

Mathematical Modeling of SOIC Package Dynamics in Dielectric Fluids during High-Voltage Insulation Testing
Document Type
article
Source
Applied Sciences, Vol 14, Iss 9, p 3693 (2024)
Subject
high-voltage testing
surface-mount devices (SMDs)
dielectric fluid hydrodynamics
SOIC package misalignment
Technology
Engineering (General). Civil engineering (General)
TA1-2040
Biology (General)
QH301-705.5
Physics
QC1-999
Chemistry
QD1-999
Language
English
ISSN
14093693
2076-3417
Abstract
The efficient testing and validation of the high-voltage (HV) insulation of small-outline integrated circuit (SOIC) packages presents numerous challenges when trying to achieve faster and more accurate processes. The complex behavior these packages when submerged in diverse physical media with varying densities requires a detailed analysis to understand the factors influencing their behavior. We propose a systematic and scalable mathematical model based on trapezoidal motion patterns and a deterministic analysis of hydrodynamic forces to predict SOIC package misalignment during automated high-voltage testing in a dielectric fluid. Our model incorporates factors known to cause misalignment during the maneuvering of packages, such as surface tension forces, sloshing, cavity formation, surface waves, and bubbles during the insertion, extraction, and displacement of devices while optimizing test speed for minimum testing time. Our model was validated via a full-factorial statistical experiment for different SOIC package sizes on a pick-and-place (PNP) machine with preprogrammed software and a zero-insertion force socket immersed in different dielectric fluids under controlled thermal conditions. Results indicate the model achieves 99.64% reliability with a margin of error of less than 4.78%. Our research deepens the knowledge and understanding of the physical and hydrodynamic factors that impact the automated testing processes of high-voltage insulator SOIC packages of different sizes for different dielectric fluids. It enables improved testing times and higher reliability than traditional trial-and-error methods for high-voltage SOIC packages, leading to more efficient and accurate processes in the electronics industry.