부산대학교 도서관

Clock routing to minimize the clock skew is very necessary to make high performance LSIs. Our clock routing method: (1) realizes the specified delay to each input terminal and provides a zero skew; (2) uses multiple routing layers for pin-to-pin routing; and (3) considers the delay arising from the resistance of a through-hole. Experimental results show that the delay is within 1% error compared to the specified delay and the skew can be controlled within pico second order.