부산대학교 도서관

In the realm of rapidly evolving technology, there is an increasing emphasis on both high resolution and low power consumption in audio-band applications of Analog-to-Digital Converter (ADC) chips. Delta-Sigma Modulators (ΔΣMs) are commonly employed in these applications for their exceptional resolution; however, they also exhibit a substantial power consumption. The core objective of this paper is to optimize the power consumption of ΔΣMs without compromising the circuit performance. In this paper, two circuits are proposed to optimize the power consumption of ΔΣMs while maintaining the performance. The first proposed circuit is a noise-shaping SAR-assisted MASH ΔΣM and the second proposed circuit is a second-order pseudo-two-path inverter-based ΔΣM. Both circuits are implemented using the UMC 180nm CMOS process with the supply voltage of 1.4V. A simulated SNDR value of 88.78 dB with a total power consumption of 128 uW is achieved by the first circuit, while the second circuit achieves a simulated SNDR value of 84.75 dB with a total power consumption of 48 uW. To achieve the optimization of power consumption, the employment of a quantizer in the form of a Successive Approximation Register ADC (SAR ADC) and the utilization of Noise-Shaping (NS) techniques are enabled by the proposed circuits. A Multi-Stage Noise-Shaping (MASH) architecture and digital filters are implemented by the first circuit, effectively eliminating excess noise. An inverter-based integrator with a pseudo-two-path structure is utilized by the second circuit to realize a second-order ΔΣM with only one integrator and maximize the efficiency of circuit components.