학술논문

A Fully Automated Environment for Verification of Virtual Prototypes
Document Type
Article
Source
EURASIP Journal on Advances in Signal Processing; December 2006, Vol. 2006 Issue: 1 p1-12, 12p
Subject
Language
ISSN
16876172; 16876180
Abstract
The extremely dynamic and competitive nature of the wireless communication systems market demands ever shorter times to market for new products. Virtual prototyping has emerged as one of the most promising techniques to offer the required time savings and resulting increases in design efficiency. A fully automated environment for development of virtual prototypes is presented here, offering maximal efficiency gains, and supporting both design and verification flows, from the algorithmic model to the virtual prototype. The environment employs automated verification pattern refinement to achieve increased reuse in the design process, as well as increased quality by reducing human coding errors.