부산대학교 도서관

A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On- and off- state capacitances ( ${C}_{\text {on}}$ and ${C}_{\text {off}}{)}$ are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 107 cycles and retention time of 104 sec.