학술논문
A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch
Document Type
Article
Author
Source
Circuits and Systems II: Express Briefs, IEEE Transactions on; September 2023, Vol. 70 Issue: 9 p3228-3232, 5p
Subject
Language
ISSN
15497747; 15583791
Abstract
This brief presents a 32x32 pseudo-ReRAM-based analog computing-in-memory (CIM) macro in 28nm CMOS. A 4b self-error-correcting word-line (WL) driver reduces the analog compute inaccuracy while minimizing the latency. A stability compensating dummy row maximizes the accumulation length of the multiply-and-accumulate (MAC). The column-sensing dual-phase 6b successive-approximation-register (SAR) analog-to-digital-converter (ADC) maximizes the through-put with minimized pitch. The proposed CIM occupies an active area of 0.0155mm 2 and consumes 4.36mW with an average energy efficiency of 25.8TOPS/W. The measured performance achieves the highest normalized throughput with an end-to-end inference accuracy comparable to FP32 with less than a 0.11% drop.