학술논문
An error-tolerant serial binary full-adder via a spiking neural P system using HP/LP basic neurons
Document Type
Article
Source
Journal of Membrane Computing; March 2020, Vol. 2 Issue: 1 p42-48, 7p
Subject
Language
ISSN
25238906; 25238914
Abstract
We present an implementation of an improved adder via a spiking neural P system. Our adder processes arbitrary length binary numbers, and thus, is suitable for cryptographic applications. Due to the use of dual-rail logic, the adder is also error tolerant. We present the implementation concept, as well as a simulation model in System-C.