학술논문
Junctionless Negative-Differential-Resistance Device Using 2D Van-Der-Waals Layered Materials for Ternary Parallel Computing.
Document Type
Academic Journal
Author
Lee T; Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, South Korea.; Jung KS; Flash Memory Technology Design Team, Samsung Electronics Co. Ltd., Giheung, 17113, South Korea.; Department of Semiconductor and Display Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, South Korea.; Seo S; Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, South Korea.; Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.; Research Laboratory of Electronics, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Lee J; Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, South Korea.; Park J; Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, 37673, South Korea.; Kang S; Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.; Park J; Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.; Kang J; Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, South Korea.; Ahn H; Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, South Korea.; Kim S; Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, South Korea.; Lee HW; Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Lee D; Research Laboratory of Electronics, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Department of Mechanical Engineering, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Kim KS; Research Laboratory of Electronics, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Department of Mechanical Engineering, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Kim H; Research Laboratory of Electronics, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Department of Mechanical Engineering, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign (UIUC), Urbana, IL, 61801, USA.; Nick Holonyak, Jr. Micro and Nanotechnology Laboratory, University of Illinois Urbana-Champaign (UIUC), Urbana, IL, 61801, USA.; Heo K; School of Semiconductor Science & Technology, Jeonbuk National University, Jeonju, 54896, South Korea.; Kim S; School of Electronics Engineering College of IT Engineering, Kyungpook National University, Daegu, 41566, South Korea.; Bae SH; Department of Mechanical Engineering and Materials Science, Washington University in Saint Louis, Missouri, MO, 63130, USA.; Institute of Materials Science and Engineering, Washington University in Saint Louis, Missouri, MO, 63130, USA.; Kang S; Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, 37673, South Korea.; Kang K; Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.; Graduate School of Semiconductor Technology, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141, South Korea.; Kim J; Research Laboratory of Electronics, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Department of Mechanical Engineering, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02138, USA.; Park JH; Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, South Korea.
Source
Publisher: Wiley-VCH Country of Publication: Germany NLM ID: 9885358 Publication Model: Print-Electronic Cited Medium: Internet ISSN: 1521-4095 (Electronic) Linking ISSN: 09359648 NLM ISO Abbreviation: Adv Mater Subsets: PubMed not MEDLINE; MEDLINE
Subject
Language
English
Abstract
Negative-differential-resistance (NDR) devices offer a promising pathway for developing future computing technologies characterized by exceptionally low energy consumption, especially multivalued logic computing. Nevertheless, conventional approaches aimed at attaining the NDR phenomenon involve intricate junction configurations and/or external doping processes in the channel region, impeding the progress of NDR devices to the circuit and system levels. Here, an NDR device is presented that incorporates a channel without junctions. The NDR phenomenon is achieved by introducing a metal-insulator-semiconductor capacitor to a portion of the channel area. This approach establishes partial potential barrier and well that effectively restrict the movement of hole and electron carriers within specific voltage ranges. Consequently, this facilitates the implementation of both a ternary inverter and a ternary static-random-access-memory, which are essential components in the development of multivalued logic computing technology.
(© 2024 The Authors. Advanced Materials published by Wiley‐VCH GmbH.)
(© 2024 The Authors. Advanced Materials published by Wiley‐VCH GmbH.)