부산대학교 도서관

This article describes innovations in the Design for Validation (DFV), Design for Test (DFT), and High Volume Manufacturing (HVM) features of the Intel® microarchitecture code name Nehalem family of products. These features are critical to debugging the complex architecture of this product family, and they are key to bringing the product family to market on schedule. The challenges we faced included dealing with new high-speed interfaces, a high level of integration, multiple cores, multi-level on-die caching, extensive architectural changes over previous architecture generations, and the integration of PCI Express (PCIe) Gen2 and graphics in client versions of the product. Test and debugging features described in this article include the test access mechanisms, mirror port technology, manufacturing test features, in-system observability hooks for debug, and survivability features used in the platform. Key debugging experiences are highlighted while showing how these features enabled a quick and predictable path through component and system debugging stages through to production. [ABSTRACT FROM AUTHOR]