부산대학교 도서관

For STM-N transmission lines in a synchronous digital hierarchy (SDH), a 24N bits interleaved parity (BIP) detection code is established in order to monitor transmission line errors. The hardware required for BIP code calculation increases in proportion to the speed of the transmission line. For example, with STM-16 (2.48832 Gbit/s), the BIP code uses 384 bits, and the line-error detection function occupies a large portion of the SDH interface hardware. This paper proposes a method to solve the foregoing problem, which implements line-error detection by using a shorter BIP code obtained by conversion of the received RIP code, at the receiving end. At the transmitting end, RIP code conforming with the ITU-T (formerly CCIIT) standard is generated. This method allows integration with inter- national standards, without degrading performance. That is, with an STM46, the hardware size is reduced by about 3000 gates, which is approximately a 20 percent reduction in the total gate count of an SDH processor. [ABSTRACT FROM AUTHOR]