학술논문
Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film.
Document Type
Article
Author
Source
Subject
*SEMICONDUCTOR wafer bonding
*WAFER-scale integration of circuits
*SURFACE tension
*OPTICAL devices
*INTEGRATED circuits
*MOLECULAR self-assembly
*MULTICHIP modules (Microelectronics)
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Language
ISSN
0018-9383
Abstract
A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 \mum when 3\,\times\,3-, 5\,\times\,5-, 4\,\times\,9,- or 10\,\times\,10-mm^2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-\mum-pitch Cu–SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu–SnAg microbumps exhibited ohmic contacts, and the resistance of \sim40~m\Omega/bump was sufficiently low for 3-D large-scale integration application. [ABSTRACT FROM AUTHOR]