소장자료
LDR | 03396cam a2200000 a | ||
001 | 0100442079▲ | ||
003 | OCoLC▲ | ||
005 | 20191218102211▲ | ||
007 | ta ▲ | ||
008 | 190827s2019 enka b 001 0 eng c▲ | ||
020 | ▼a9780135732410 (pbk.)▲ | ||
020 | ▼a0135732417▲ | ||
035 | ▼a(OCoLC)1114265995▲ | ||
040 | ▼aIWA▼beng▼cIWA▼dYDXIT▼dSOI▼dOCLCF▼dMEAUC▲ | ||
082 | 0 | 4 | ▼a621.39/5▼223▲ |
090 | ▼a621.395▼bD578v▲ | ||
100 | 1 | ▼aDillinger, Thomas E.,▼d1956-▲ | |
245 | 1 | 0 | ▼aVLSI design methodology development /▼cThomas Dillinger.▲ |
246 | 3 | ▼aVery large scale integration design methodology development▲ | |
260 | ▼aLondon :▼bPearson,▼c2019.▲ | ||
300 | ▼axvii, 734 p. :▼bill. ;▼c24 cm.▲ | ||
504 | ▼aIncludes bibliographical references and index.▲ | ||
505 | 0 | ▼aIntroduction -- VLSI Design methodology -- Hierarchical design decomposition -- Cell and IP modeling -- Characteristics of functional validation -- Characteristics of formal equivalency verification -- Logic synthesis -- Placement -- Routing -- Layout parasitic extraction and electrical modeling -- Timing analysis -- Noise analysis -- Power analysis -- Power rail voltage drop analysis -- Electromigration (EM) reliability analysis -- Miscellaneous electrical analysis requirements -- ECOs -- Physical design verification -- Design for testability analysis -- Preparation for tapeout -- Post-silicon debug and characterization ("bring-up") and product qualification.▲ | |
520 | ▼aAs microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design. Microprocessor design authority Tom Dillinger carefully introduces core concepts, and then guides engineers through modeling, functional design validation, design implementation, electrical analysis, and release to manufacturing. Writing from the engineer's perspective, he covers underlying EDA tool algorithms, flows, criteria for assessing project status, and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. This guide is for all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. It is applicable to engineering teams undertaking new projects and migrating existing designs to new technologies.▲ | ||
650 | 0 | ▼aIntegrated circuits▼xVery large scale integration.▲ | |
650 | 0 | ▼aIntegrated circuits▼xVery large scale integration▼xTesting.▲ | |
650 | 0 | ▼aMicroelectronics.▲ |
VLSI design methodology development
자료유형
국외단행본
서명/책임사항
VLSI design methodology development / Thomas Dillinger.
다양한 서명
Very large scale integration design methodology development
발행사항
London : Pearson , 2019.
형태사항
xvii, 734 p. : ill. ; 24 cm.
서지주기
Includes bibliographical references and index.
내용주기
Introduction -- VLSI Design methodology -- Hierarchical design decomposition -- Cell and IP modeling -- Characteristics of functional validation -- Characteristics of formal equivalency verification -- Logic synthesis -- Placement -- Routing -- Layout parasitic extraction and electrical modeling -- Timing analysis -- Noise analysis -- Power analysis -- Power rail voltage drop analysis -- Electromigration (EM) reliability analysis -- Miscellaneous electrical analysis requirements -- ECOs -- Physical design verification -- Design for testability analysis -- Preparation for tapeout -- Post-silicon debug and characterization ("bring-up") and product qualification.
요약주기
As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design. Microprocessor design authority Tom Dillinger carefully introduces core concepts, and then guides engineers through modeling, functional design validation, design implementation, electrical analysis, and release to manufacturing. Writing from the engineer's perspective, he covers underlying EDA tool algorithms, flows, criteria for assessing project status, and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. This guide is for all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. It is applicable to engineering teams undertaking new projects and migrating existing designs to new technologies.
주제
ISBN
9780135732410 (pbk.) 0135732417
청구기호
621.395 D578v
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