학술논문
Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing
Document Type
Conference
Author
Fischer, K.; Agostinelli, M.; Allen, C.; Bahr, D.; Bost, M.; Charvat, P.; Chikarmane, V.; Fu, Q.; Ganpule, C.; Haran, M.; Heckscher, M.; Hiramatsu, H.; Hwang, E.; Jain, P.; Jin, I.; Kasim, R.; Kosaraju, S.; Lee, K. S.; Liu, H.; McFadden, R.; Nigam, S.; Patel, R.; Pelto, C.; Plekhanov, P.; Prince, M.; Puls, C.; Rajamani, S.; Rao, D.; Reese, P.; Rosenbaum, A.; Sivakumar, S.; Song, B.; Uncuer, M.; Williams, S.; Yang, M.; Yashar, P.; Natarajan, S.
Source
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM) Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), 2015 IEEE International. :5-8 May, 2015
Subject
Language
ISSN
2380-632X
2380-6338
2380-6338
Abstract
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple layers (M4 and M6) incorporate an air gap integration scheme to deliver up to 17% RC benefit. Pitch Division patterning is introduced to deliver high yield capable interconnect layers with a minimum pitch of 52nm.