학술논문
An analysis of stress evolution in stacked GAA transistors
Document Type
Conference
Author
Source
2016 IEEE Silicon Nanoelectronics Workshop (SNW) Silicon Nanoelectronics Workshop (SNW), 2016 IEEE. :206-207 Jun, 2016
Subject
Language
Abstract
We used Finite Element Method to evaluate the stress evolution along a FEOL integration in Gate-All-Around transistors of stacked channels configuration. Hypothesis are done about the materials behavior and dimensions for 5 nm node to evaluate the upper and lower stress limits due to source and drain stressor effect. For the most probable configuration, slightly tensile Si channels are obtained either for pMOS and nMOS. Alternative solutions for stressing the channel in NS configuration would be essential.