부산대학교 도서관

The nature and heterogeneity of modern workloads force hardware designers to choose between general-purpose processors, which come with superior flexibility, and highly-tailored accelerators that boost performance and power efficiency at the cost of extreme specialization. One of the most promising solutions that couple the flexibility of a processor with the performance and efficiency of an accelerator is the vector processor architecture. Since RISC-V has only recently frozen its vector ISA extension, no open-source RISC-V-based vector processor has been fabricated and characterized. This brief presents the Yun SoC, featuring the first implementation of an open-source RISC-V-based vector processor in TSMC’s 65-nm technology. Our efficient 4-lane design achieves almost peak theoretical performance on large matrix multiplication problems with an FPU utilization of almost 90%. Yun, with a critical path of 30 FO4 inverter delays, achieves a peak performance of 2.83 GFLOPSDP (at 400 MHz and 1.5 V), a leading-edge area efficiency of 3 GFLOPSP/cycle/MGE, and a peak energy efficiency of 10.8 GFLOPSDP (at 100 MHz and 0.85 V). Yun supports integer (64-bit, 32-bit, 16-bit, and 8-bit)) and floating-point (64-bit and 32-bit) SIMD data formats, as required by ML and data analytics workloads.