부산대학교 도서관

Flexible manufacturing of ICs depends on technology computer-aided design (TCAD) tools. As ICs scale, contamination effects become more significant. Metal ions are a major source of poor electrical performance in solid state devices causing increased junction leakage, oxide breakdown strength degradation and metal-oxide-semiconductor (MOS) capacitor leakage which adversely affect the function of ultra large scale integrated (ULSI) circuits. It is important to know the level of contamination that is low enough to be acceptable for a particular application and how effective the wafer cleaning strategies are. There is a need for TCAD tools that include microcontamination effects to produce viable processes for the deep submicron era. This paper describes a concept for integrating contamination effects into the Silvaco VWF Software for the specific case of metals deposited from process solutions. Initial feasibility of the concept is demonstrated by comparison of experimental results from devices fabricated with an intentionally contaminated process with results from simulations for that process.