학술논문
High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
Document Type
Conference
Author
Packan, P.; Akbar, S.; Armstrong, M.; Bergstrom, D.; Brazier, M.; Deshpande, H.; Dev, K.; Ding, G.; Ghani, T.; Golonzka, O.; Han, W.; He, J.; Heussner, R.; James, R.; Jopling, J.; Kenyon, C.; Lee, S-H.; Liu, M.; Lodha, S.; Mattis, B.; Murthy, A.; Neiberg, L.; Neirynck, J.; Pae, S.; Parker, C.; Pipes, L.; Sebastian, J.; Seiple, J.; Sell, B.; Sharma, A.; Sivakumar, S.; Song, B.; St. Amour, A.; Tone, K.; Troeger, T.; Weber, C.; Zhang, K.; Luo, Y.; Natarajan, S.
Source
2009 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2009 IEEE International. :1-4 Dec, 2009
Subject
Language
ISSN
0163-1918
2156-017X
2156-017X
Abstract
A 32nm logic technology for high performance microprocessors is described. 2 nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um I off . PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um I off . The impact of SRAM cell and array size on Vccmin is reported.