학술논문

A novel CMOS monolithic active pixel sensor with analog signal processing and 100% fill factor
Document Type
Conference
Source
2007 IEEE Nuclear Science Symposium Conference Record Nuclear Science Symposium Conference Record, 2007. NSS '07. IEEE. 2:931-935 Oct, 2007
Subject
Nuclear Engineering
Power, Energy and Industry Applications
Fields, Waves and Electromagnetics
Engineered Materials, Dielectrics and Plasmas
CMOS process
Signal processing
CMOS image sensors
Pixel
Diodes
CMOS technology
Charge-coupled image sensors
Circuit testing
Manufacturing
Active circuits
Language
ISSN
1082-3654
Abstract
We have designed and fabricated a CMOS Monolithic Active Pixel Sensor (MAPS) in a novel 0.18 micrometer image-sensor technology (INMAPS) which has a 100% fill factor for charged particle detection and full CMOS electronics in the pixel. The first test sensor using this technology was received from manufacture in July 2007. The key component of the INMAPS process is the implementation of a deep p-well beneath the active circuits. A conventional MAPS design for charged-particle imaging will experience charge sharing between the collection diodes and any PMOS active devices in the pixel which can dramatically reduce the efficiency of the pixel. By implementing a deep p-well, the charge deposited in the epitaxial layer is reflected and conserved for collection at only the exposed collection diode nodes. We have implemented two pixel architectures for charged particle detection. The target application for these pixels is for the sensitive layers of an electromagnetic calorimeter (ECAL) in an International Linear Collider (ILC) detector. Both pixel architectures contain four n-well diodes for charge-collection; analog front-end circuits for signal pulse shaping; comparator for threshold discrimination; digital logic for threshold trim adjustment and pixel masking. Pixels are served by shared row-logic which stores the location and time-stamp of pixel hits in local SRAM, at the bunch crossing rate of the ILC beam. The sparse hit data are read out from the columns of logic after the bunch train. Here we present design details and preliminary results.