학술논문
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
Document Type
Conference
Author
Source
2017 Symposium on VLSI Technology VLSI Technology, 2017 Symposium on. :T212-T213 Jun, 2017
Subject
Language
ISSN
2158-9682
Abstract
Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing on transistor parameters, such as V t and gate stack, defines an upper process boundary and translates to with-in-die (WID V t variation. Combining DB laser annealing technique with process-friendly layouts enables contact resistance benefit without degrading product level variability.