학술논문
A low power all-digital PLL with power optimized digitally controlled oscillator
Document Type
Conference
Author
Source
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of. :1-4 Dec, 2010
Subject
Language
Abstract
This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13µm CMOS process. Chip measurement results show that the total circuit occupies 0.083mm 2 area, and the DCO power dissipation was optimized to 2.83mW at the output frequency of 600MHz. The power optimized DCO is implemented in ADPLL and save the overall power dissipation of ADPLL.