학술논문
5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing Applications
Document Type
Conference
Author
Yeap, Geoffrey; Lin, S. S.; Chen, Y. M.; Shang, H. L.; Wang, P. W.; Lin, H. C.; Peng, Y. C.; Sheu, J. Y.; Wang, M.; Chen, X.; Yang, B. R.; Lin, C. P.; Yang, F. C.; Leung, Y. K.; Lin, D. W.; Chen, C. P.; Yu, K. F.; Chen, D. H.; Chang, C. Y.; Chen, H. K.; Hung, P.; Hou, C. S.; Cheng, Y. K.; Chang, J.; Yuan, L.; Lin, C. K.; Chen, C. C.; Yeo, Y. C.; Tsai, M. H.; Lin, H. T.; Chui, C. O.; Huang, K. B.; Chang, W.; Lin, H. J.; Chen, K. W.; Chen, R.; Sun, S. H.; Fu, Q.; Yang, H. T.; Chiang, H. T.; Yeh, C. C.; Lee, T. L.; Wang, C. H.; Shue, S. L.; Wu, C. W.; Lu, R.; Lin, W. R.; Wu, J.; Lai, F.; Wu, Y. H.; Tien, B. Z.; Huang, Y. C.; Lu, L. C.; He, Jun; Ku, Y.; Lin, J.; Cao, M.; Chang, T. S.; Jang, S. M.
Source
2019 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2019 IEEE International. :36.7.1-36.7.4 Dec, 2019
Subject
Language
ISSN
2156-017X
Abstract
A leading edge 5nm CMOS platform technology has been defined and optimized for mobile and HPC applications. This industry-leading 5nm technology features, for the first time, full-fledged EUV, and high mobility channel (HMC) finFETs with densest 0.021µm 2 HD SRAM. This true 5nm CMOS platform technology is a full node scaling from our successful 7nm node [4] in offering ~1.84x logic density, 15% speed gain or 30% power reduction. The 5nm platform technology successfully passed qualification [3] with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks. Currently in risk production, this true 5nm platform technology is on schedule for high volume production in 1H 2020.