학술논문

Two-Step Spike Encoding Scheme and Architecture for Highly Sparse Spiking-Neural-Network
Document Type
Conference
Source
2024 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2024 IEEE International Symposium on. :1-5 May, 2024
Subject
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Maximum likelihood estimation
Accuracy
Throughput
Encoding
Hardware
Generators
Energy efficiency
Spiking-Neural-Network (SNN)
Rate Encoding
SNN Accelerator
Sparsity
Language
ISSN
2158-1525
Abstract
This paper proposes a two-step spike encoding, which consists of the source encoding and process encoding for energy-efficient spiking-neural-network (SNN) acceleration. The eigen-train generation and its superposition generate spike trains which show high accuracy with low spike ratio. Sparsity boosting (SB) and spike generation skipping (SGS) reduce the number of operations for SNN. Time shrinking multi-level encoding (TS-MLE) compresses the number of spikes in a train along time axis, and spike-level clock skipping (SLCS) decreases the processing time. Eigen-train generation achieves 90.3% accuracy, the same accuracy as CNN, under the condition of 4.18% spike ratio for CIFAR-10 classification. SB reduces spike ratio by 0.49× with only 0.1% accuracy loss, and the SGS reduces the spike ratio by 20.9% with 0.5% accuracy loss. TS- MLE and SLCS increase the throughput of SNN by 2.8× while decreasing the hardware resource for spike generator by 75% compared with previous generators.