학술논문
Exploring regular fabrics to optimize the performance-cost trade-off
Document Type
Conference
Author
Source
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Design automation conference Design Automation Conference, 2003. Proceedings. :782-787 2003
Subject
Language
Abstract
While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.