학술논문

Enabling Normally-Off In Situ Computing With a Magneto-Electric FET-Based SRAM Design
Document Type
Periodical
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 71(4):2742-2748 Apr, 2024
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Transistors
Switches
Nonvolatile memory
Logic gates
Computer architecture
Magnetic tunneling
Resistance
Magneto-electric field-effect transistor (MEFET)
normally-OFF computing
processing-in-SRAM
Language
ISSN
0018-9383
1557-9646
Abstract
As an emerging post-CMOS Field Effect Transistor, magneto-electric field-effect transistors (MEFETs) offer compelling design characteristics for logic and memory applications, such as high-speed switching, low power consumption, and nonvolatility. In this article, for the first time, a nonvolatile MEFET-based SRAM design named ME-SRAM is proposed for edge applications which can remarkably save the SRAM static power consumption in the idle state through a fast backup-restore process. To enable normally- OFF in situ computing, the ME-SRAM cell is integrated into a novel processing-in-SRAM architecture that exploits a hardware-optimized bitline computing approach for the execution of Boolean logic operations between operands housed in a memory sub-array within a single clock cycle. Our device-to-architecture evaluation results on Binary convolutional neural network acceleration show the robust performance of ME-SRAM while reducing energy consumption on average by a factor of $\sim 5.3\times $ compared to the best in-SRAM designs.