학술논문
A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC
Document Type
Conference
Author
Source
2023 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2023 IEEE International Symposium on. :1-5 May, 2023
Subject
Language
ISSN
2158-1525
Abstract
This paper presents a novel architecture of a SAR assisted 2 step ADC where the SAR residue is quantized with a bidirectional digital slope time-based converter. The bidirectional slope halves the conversion time of the second stage. Furthermore, the redundancy requirements in the second stage are considerably reduced through a unified global calibration scheme. A practical example is given for a 12-bit 64 MS/s ADC with 67 dB SNDR and $\mathbf{208}\ \boldsymbol{\mu} \mathbf{W}$ estimated power consumption targeted at ultra-low power RF receivers. The complete architecture including calibration has been validated with VerilogA models including capacitor mismatch, comparator offsets and noise.