학술논문
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors
Document Type
Conference
Author
Source
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) Design automation conference Design Automation Conference, 2002. Proceedings. 39th. :486-491 2002
Subject
Language
ISSN
0738-100X
Abstract
We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5/spl times/ larger computation runtime than iSTATS due to its iterative nature.