학술논문
Response Speed of Negative Capacitance FinFETs
Document Type
Conference
Author
Source
2018 IEEE Symposium on VLSI Technology VLSI Technology, 2018 IEEE Symposium on. :49-50 Jun, 2018
Subject
Language
ISSN
2158-9682
Abstract
We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.