학술논문

The fast tracker processor for hadronic collider triggers
Document Type
Conference
Source
2000 IEEE Nuclear Science Symposium. Conference Record (Cat. No.00CH37149) Nuclear science symposium Nuclear Science Symposium Conference Record, 2000 IEEE. 2:12/135-12/140 vol.2 2000
Subject
Nuclear Engineering
Power, Energy and Industry Applications
Fields, Waves and Electromagnetics
Engineered Materials, Dielectrics and Plasmas
Roads
Detectors
Logic
Pattern recognition
Hardware
Pipeline processing
Silicon
Delay
Associative memory
Collision mitigation
Language
ISSN
1082-3654
Abstract
Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above few GeV and search secondary vertexes within typical level-2 times.