부산대학교 도서관

This paper presents a high-speed topology for phase counter in an All-digital phase-locked loop (ADPLL) architectures. The structure, called Variable Phase Accumulator (VP AC) is a digital block running at the highest frequency in the ADPLL. The high operating speed feature of the architecture is obtained by exploiting the count output in the reference frequency domain while the circuit needs to handle the radio frequency (RF) signal from the oscillator output. The enhanced topology decreases the timing critical path and minimizes the hardware logic in the highest frequency domain to a shift register encoding only four states. Indeed, a simple logic gate is used to slow the count process. The proposed circuit is demonstrated in 90-nm CMOS process., which allows having a power save of about 20 times the power of a conventional counter without penalty in silicon area or frequency running.