학술논문
Gatestacks for scalable high-performance FinFETs
Document Type
Conference
Author
Vellianitis, G.; Van Dal, M.J.H.; Witters, L.; Curatola, G.; Doornbos, G.; Collaert, N.; Jonville, C.; Torregiani, C.; Lai, L.-S.; Petry, J.; Pawlak, B.J.; Duffy, R.; Demand, M.; Beckx, S.; Mertens, S.; Delabie, A.; Vandeweyer, T.; Delvaux, C.; Leys, F.; Hikavyy, A.; Rooyackers, R.; Kaiser, M.; Weemaes, R.G.R.; Voogt, F.; Roberts, H.; Donnet, D.; Biesemans, S.; Jurczak, M.; Lander, R.J.P.
Source
2007 IEEE International Electron Devices Meeting Electron Devices Meeting, 2007. IEDM 2007. IEEE International. :681-684 Dec, 2007
Subject
Language
ISSN
0163-1918
2156-017X
2156-017X
Abstract
Excellent performance (995μA/μm at I off =94nA/μm and V dd =1V) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193nm immersion lithography and dry etch. PVD TiN electrodes on HfSiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage V T variability is shown to explain this dependence upon fin width and gate length.