학술논문
Tri-gate In0.53Ga0.47As-on-insulator junctionless field effect transistors
Document Type
Conference
Author
Source
EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on. :97-100 Jan, 2015
Subject
Language
Abstract
A tri-gate In 0.53 Ga 0.47 As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture is demonstrated. The devices feature a 20-nm-thick n-In 0.53 Ga 0.47 As channel doped to 10 18 /cm 3 obtained by direct wafer bonding and a 3.5-nm-thick A1 2 O 3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The impact of the fin width (W fin ) and gate length (L g ) scaling at fixed channel doping (N d ) and equivalent oxide thickness (EOT) on the device performance is discussed and benchmarked.