학술논문

Study on Potassium Contamination in SOI Wafer Fabrication Using Dynamic SIMS
Document Type
Conference
Source
2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits Physical and Failure Analysis of Integrated Circuits, 2006. 13th International Symposium on the. :133-136 Jul, 2006
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
General Topics for Engineers
Contamination
Fabrication
CMOS technology
Built-in self-test
Silicon on insulator technology
Integrated circuit noise
Isolation technology
CMOS integrated circuits
High speed integrated circuits
FETs
Language
ISSN
1946-1542
1946-1550
Abstract
In this paper, a case study of BIST failure in SOI wafer fabrication was presented. With optimized charge neutralization using a well-controlled normal incident electron beam, a reliable depth distribution of K in the ILD was obtained which is helpful to understand the source of K contamination. From the SIMS and EDX results, the root cause was concluded to be K contamination introduced by the CMP slurry. The yield has been improved greatly by depositing a layer of high density oxide on the top of ILD to block the K contamination