부산대학교 도서관

Packing is a required step in a typical FPGA CAD flow, with high impacts on FPGA placement and routing. Early prediction of packing results can guide design optimization and expedite design closure. In this brief, we propose an imbalanced large graph learning framework, ImLG, to predict whether logic elements will be packed after placement. Specifically, we propose dedicated feature extraction and aggregation methods to enhance the node representation learning of circuit graphs. With imbalanced distribution of packed and unpacked logic elements, we further propose techniques such as graph oversampling and mini-batch training for this imbalanced learning task in large circuit graphs. Experimental results demonstrate that our framework can improve the F1-score by $\boldsymbol {42.82\%}$ compared to the most recent Gaussian-based prediction method. Physical design results show that the proposed method can assist the placer in improving routed wirelength by $\boldsymbol {0.93\%}$ , and SLICE occupation by $\boldsymbol {0.89\%}$ .