부산대학교 도서관

Because of its In-Memory-Computation (IMC) capacity and low area footprint, memristive technology is a rapidly growing alternative to traditional computer architectures. Using IMPLY logic, this research proposes an efficient multi-bit comparator architecture in memristor technology. This article proposes three one-bit comparator designs, two of which conduct serial computations and the other performs parallel computations. An area efficient comparator design takes only four memristors to make the comparison in thirteen computational steps by reusing the input memristors. When the number of memristors that are reused decreases, the design speed increases. This is seen in the second serial comparator design, which computes the result in only eight steps using six memristors. A comparator design with seven memristors that performs the parallel computations takes only six steps to compute the output. The proposed method can be extended to multi-bit designs. A two-bit high speed comparator is also proposed, which takes twenty-two steps to perform the magnitude comparison. The proposed comparator designs were simulated in the Cadence Virtuoso using the VTEAM model.