학술논문
Trigate 6T SRAM scaling to 0.06 µm2
Document Type
Conference
Author
Guillorna, M.; Chang, J.; Pyzyna, A.; Engelmann, S.; Joseph, E.; Fletcher, B.; Cabral, C.; Lin, C.-H.; Bryant, A.; Darnon, M.; Ott, J.; Lavoie, C.; Frank, M.; Gignac, L.; Newbury, J.; Wang, C.; Klaus, D.; Kratschmer, E.; Bucchignano, J.; To, B.; Graham, W.; Lauer, I.; Sikorski, E.; Carter, S.; Narayanan, V.; Fuller, N.; Zhang, Y.; Haensch, W.
Source
2009 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2009 IEEE International. :1-3 Dec, 2009
Subject
Language
ISSN
0163-1918
2156-017X
2156-017X
Abstract
We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 µm 2 . This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated with planar devices [1].