학술논문

Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs
Document Type
Periodical
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 43(7):2151-2162 Jul, 2024
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Timing
Predictive models
Integrated circuit modeling
Data models
Linear regression
Design automation
Bayes methods
Active learning
Bayesian decision theory
featured engineering
Gaussian process
machine learning
multiprocess corners
static timing analysis (STA)
Language
ISSN
0278-0070
1937-4151
Abstract
We propose a multicorner multistage timing analysis prediction framework using a generalized linear model with latent features. We then further improve such methods using kernel trick extension, transfer learning with knowledge from previous designs, and multioutput feature engineering to deliver state-of-the-art (SOTA) prediction accuracy with very limited training data. Most importantly, our method is equipped with a Bayesian decision strategy to deliver reliable predictions with accuracy close to 100%, pushing the frontier of the machine-learning-based static timing analysis (STA) for practical implementation in the industry environment, where reliability is highly desired. Experimental results show that the accuracy of our proposed method outperforms the SOTA competitors by up to 4x and can improve prediction accuracy to 100% with little extra STA executions.