부산대학교 도서관

In order to reduce the power consumption and hardware resource consumption of deploying YOLO algorithms on embedded devices, we designed a low-power YOLOv4-Tiny algorithm accelerator based on FPGA. Firstly, we introduced an attention mechanism into the FPN module of the YOLOv4-Tiny algorithm and effectively trained the improved model on a computer platform, utilizing 16-bit fixed-point quantization and layer fusion to reduce the model's computational load. Secondly, based on the FPGA hardware platform, we maximized the use of techniques such as pipelining, loop unrolling, and ping-pong operations to design hardware accelerators for speeding up computationally intensive units such as convolutional and pooling layers in the YOLOv4-Tiny algorithm. Finally, we completed the hardware system design for the entire algorithm. The experimental results show that our improved algorithm improves the mean Average Precision (map) by 1.9% on the MS COCO dataset. When the clock frequency of FPGA development board is 150 MHz, the total power consumption of our improved algorithm in the hardware system is only 3.415W. At the same time, the performance per watt reaches 6.76 GOPS/W, which is 23.3 times of the CPU platform and 10.9 times of the GPU platform of the same algorithm. The system can significantly reduce hardware resource consumption and power consumption.